dilbert
Full Member
Registered Linux User #306113
Posts: 223
|
Post by dilbert on Dec 4, 2007 23:03:45 GMT -5
FFFB: is it in rom or ram? on a C128 in bank 0.
|
|
|
Post by Robin Harbron on Dec 5, 2007 1:33:09 GMT -5
|
|
dilbert
Full Member
Registered Linux User #306113
Posts: 223
|
Post by dilbert on Dec 8, 2007 16:56:29 GMT -5
thanks for the links. i take it that FFFB is in ram.(i.e. but is a jump table to ROM) correct assumption?
|
|
|
Post by Robin Harbron on Dec 8, 2007 18:24:38 GMT -5
i take it that FFFB is in ram.(i.e. but is a jump table to ROM) Not quite. Are you familiar with how memory mapping works on the C-64? The C-128 is similar, but has a few more tricks. Anyway, the C-128's processor can only see 64k at a time, from address $0000 to $FFFF. But obviously with 128K of RAM, a bunch of ROM (somewhere around 40k worth for regular 128 mode), memory mapped registers for video, sound, i/o etc. it's going to need some trick to get at it all. So different parts of RAM, ROM and I/O can be mapped to different areas in the 64K space. By default, the KERNAL ROM is mapped to $FFFB. But with a poke or two, you can put RAM in that place as well. Issue #7 of Commodore Hacking has an excellent article on C-64 memory management. You might want to have a look at that to understand more of the theory. Maybe someone else knows of a good article online about C-128 memory management.
|
|
dilbert
Full Member
Registered Linux User #306113
Posts: 223
|
Post by dilbert on Dec 10, 2007 16:03:16 GMT -5
Are you familiar with how memory mapping works on the C-64? The C-128 is similar,..... no. So different parts of RAM, ROM and I/O can be mapped to different areas in the 64K space. This is the trick I need to understand. How is it done? I'm use to just a flat 64k map with every thing in its own place. I don't understand how it its done to write "thur" ROM to ram , etc. switching the ram to ROM ? Mapping? OK after rereading: The 6510 MPU has an integrated I/O port with six I/O lines. This port is accessed through the memory locations 0 and 1. The location 0 is the Data Direction Register for the Peripheral data Register, which is mapped to the other location. When a bit in the DDR is set, the corresponding PR bit controls the state of a corresponding Peripheral line as an output. When it is clear, the state of the Peripheral line is reflected by the Peripheral register. The Peripheral lines are numbered from 0 to 5, and they are mapped to the DDR and PR bits 0 - 5, respectively. The 8502 processor, which is used in the Commodore 128, has seven Peripheral lines in its I/O port. The seventh line is connected to the Caps lock or ASC/CC key.
I take it that the "magic"is in here....... Memory management(early) via contorol lines ! Okay, more study for me.. ;D
|
|